1. Field of the Invention
This invention relates to ElectroStatic Discharge (ESD) protection for integrated circuits and more particularly to series connected diode strings employed for ESD protection.
2. Description of Related Art
ElectroStatic Discharge (ESD) has been a serious reliability concern with respect to CMOS types of integrated circuit (IC) devices. As CMOS technology progresses into the deep sub-micron scale, the use of advanced processes such as thinner gate oxide, shorter channel length, shallower junction depth, LDD (Lightly-Doped Drain) structure, and salicide (Self-Aligned Silicide) diffusion is employed. The disadvantage of use of these processes on this extremely small scale is that there is serious degradation of the robustness of CMOS IC devices in avoiding of problems associated with ESD. In order to obtain suitable high robustness against damage from ESD, a CMOS IC must incorporate ESD protection circuits at every input and output pin. Nevertheless some unexpected ESD damage occurs in the internal circuits of CMOS IC devices beyond the input or output ESD protection circuits [1]-[6]. Even the parasitic capacitance and resistance along the power lines of an IC can also cause a negative impact on the ESD reliability of the CMOS IC [4]-[6].
As stress induced ESD effects may occur in response to positive or negative voltage on an input (or output) pin with respect to the grounded VDD or VSS pins, there are four different ESD stress combinations at each input (output) pin as shown in FIGS. 1A-1D [7]. Referring to FIGS. 1A-1D, a CMOS IC 10 which is housed within a dual-in-line package 12 having input/output pins 14 includes VDD pin 14a and VSS pin 14b. 
Since ESD voltages may have positive or negative polarities on a pad associated with the VDD or the VSS pins 14a, 14b, there are four different ESD-stress mode conditions. FIGS. 1A-1D show modes of test combinations for ESD stress on an input (or output) pin with respect to the grounded VDD or VSS pins. FIG. 1A shows the PS-mode. FIG. 1B shows the NS-mode. FIG. 1C shows the PD-mode. FIG. 1D shows the NS-mode. Therefore input and output ESD protection circuits are designed to bypass the ESD current from the stress pin to the VDD or VSS pins.
(1) PS mode: ESD stress at a pin 14c with positive voltage polarity to the grounded VSS (GND) pin 14b when VDD pin 14a and other input/output pins 14 are floating (FIG. 1A);
(2) NS mode: ESD stress at a pin 14c with negative voltage polarity to the grounded VSS. (GND) pin 14b when VDD pin 14a and other input/output pins 14 are floating (FIG. 1B).
(3) PD mode: ESD stress at a pin 14c with positive voltage polarity to the grounded VDD pin 14a when VSS (GND) pin 14b and other input/output pins 14 are floating (FIG. 1C).
(4) ND mode: ESD stress at a pin 14c with negative voltage polarity to the grounded VDD pin 14a when VSS (GND) pin 14b and other input/output pins 14 are floating (FIG. 1D).
For comprehensive ESD testing, additional ESD stress combinations are shown in FIGS. 2A-2D. These four additional ESD-testing combinations are used to verify the whole-chip ESD reliability. These additional ESD stress combinations have been specified in the ESD testing standard to verify the whole-chip ESD reliability [7].
FIGS. 2A and 2B show the pin-to-pin ESD stress with the ESD voltage being applied to an input (or output) pin while all other input and output pins except for the VDD and VSS pins 14a/14b are grounded.
FIGS. 2C and 2D show the VDD-to-VSS ESD stress with the ESD voltage being directly applied to the VDD pin 14a with the VSS pin 14b grounded while all input and output pins are floating. The additional ESD testing combinations of FIGS. 2A-2D often lead to more complex ESD current paths from the power lines to internal circuits, which causes some unexpected damage to the internal circuits in spite of providing input and output ESD protection circuits in the IC devices [8]-[10].
FIG. 3 shows ESD current discharging paths in an IC during pin-to-pin ESD stress conditions. In particular, the pin-to-pin ESD stress, as shown in FIG. 3, often causes some unexpected ESD damage located in the internal circuits, rather than damaging the input or output ESD protection circuits. In FIG. 3, a positive ESD voltage is applied to an input pin IP with an output pin OP being grounded, while the VDD and VSS pins are both floating. The ESD current is diverted from the input pad IP to the floating VDD power line through the forward-biased diode D2, above diode D1, in the input ESD protection circuit. The ESD current flowing through the VDD power line can be diverted into the internal circuit INT through a connection to the VDD line. Then, the ESD current, which is discharged through the internal circuit INT, may cause random ESD damage in the internal circuit INT, along the Path_1 current path shown as dotted line in FIG. 3.
If there is an ESD clamp circuit CC, in parallel with the internal circuit INT, across the power rails comprising VDD power line and VSS ground line, the ESD current can be discharged through the Path_2 current path shown in FIG. 3. Therefore, the internal circuit INT can be safely protected against ESD damage. Thus, an efficient ESD clamp circuit between the power supplies is necessary to protect the internal circuit INT against ESD damage [11]-[16].
In summary, in FIG. 3 the ESD current discharging paths are shown in an IC during a pin-to-pin ESD stress condition. If the IC has no ESD clamp circuit CC between the power rails (VDD power line and VSS ground line), the ESD current is discharged through the Path_1, which often causes ESD damage to the internal circuit INT. If the IC has an effective ESD clamp circuit CC between the VDD and VSS power rails, the ESD current is discharged through the Path_2.
2.1. The Diode String
Because a diode in the forward-biased condition can sustain a much higher ESD level than it can in the reverse-biased condition, a diode string with multiple cascaded diodes is therefore provided to clamp the ESD overstress voltage on the 3.3 Volts/5 Volts tolerant I/O pad [12] or between the mixed-voltage power lines [13]-[15].
FIG. 4A is a schematic circuit diagram which illustrates a PNP-based circuit 16 which incorporates a diode string D1, D2, . . . , Dnxe2x88x921, Dn of diodes connected in series from power rail VDD to ground rail VSS. The circuit 16 is used as the ESD clamp from the power rail VDD to VSS power rail.
FIG. 4B is a cross-sectional view showing a device 16xe2x80x2 which is an embodiment of the circuit 16 of FIG. 4A. Diode string D1, D2, . . . , Dnxe2x88x921, Dn is formed in a P-substrate 18 with the diodes formed in N-wells in substrate 18 which contains CMOS devices, not shown for convenience of illustration.
Each diode D1, D2, . . . , Dnxe2x88x921, Dn forms a parasitic vertical PNP transistor S1, S2, . . . , Snxe2x88x921, Sn with P-substrate 18 in a common collector configuration. The required number xe2x80x9cnxe2x80x9d, which is a positive integer, of diodes in the diode string of FIGS. 4A and 4B depends on three parameters, the leakage current ILeakage allowed at maximum operating voltage and temperature, the parasitic vertical PNP xcex2 gain, and the blocking voltage across the diode string. These relationships have been reported earlier [13]-[15]. The relevant equations are presented in the following:                                           V            String                    ⁡                      (            I            )                          =                              mV            D                    -                                    nV              T                        xc3x97                          [                                                m                  ⁡                                      (                                          m                      -                      1                                        )                                                  2                            ]                        xc3x97                          ln              ⁡                              (                                  β                  +                  1                                )                                                                        (        1        )            xe2x80x83VD(I)=nVTxc3x97(I/AIS)xe2x80x83xe2x80x83(2)
ID=AIs(eV/nVTxe2x88x921)xe2x80x83xe2x80x83(3)
VD(T1)=nEg0+(T1/T0)xc3x97(VD(T0)xe2x88x92nEg0/q)xe2x80x83xe2x80x83(4)
where
Vstring=total voltage drop across m diodes,
VD=forward turn-on voltage of one diode,
ID=forward current through the diode,
VT=KT/q called the thermal voltage
(q=electron charge),
(K=Boltzmann""s constants)
(T=absolute temperature),
n=ideality factor,
xcex2=beta gain of a parasitic PNP transistor,
Is=saturation current of a P-N junction diode,
A=area of the P-N junction diode,
m=the number of diodes in the string, and
Eg0=the extrapolated bandgap of silicon (Si) at temperature of 0xc2x0 K=1.206 eV.
Equation (1) shows that if the xcex2 gain is nearly zero, then cascading of diodes in the diode string D1, D2, . . . , Dnxe2x88x921, Dn leads to a linear increase in the turn-on voltage drop across the diode string when more diodes are cascaded. However, if the xcex2 gain is even 1 or larger, the addition of diodes does not linearly increase the voltage drop across the diode string, but causes more leakage to the substrate. This means that more diodes would be needed to support the same voltage at a specified current when the xcex2 gain of the parasitic vertical PNP increases. The I-V relation of a single diode in the forward-biased condition is shown in equation (2) and equation (3), where the forward current increases exponentially as the forward voltage of the diode increases. From equation (1)-equation (3), the main issue of the PNP-based diode string used as the VDD-to-VSS ESD clamp circuit is the leakage current, where the amplification effect of multi-stage Darlington beta (xcex28) gain will cause more leakage current through VDD to the P-substrate which is biased at VSS.
If the voltage difference between VDD and VSS becomes larger, the leakage current increases exponentially as seen in equation (3). Thus, more diodes must be inserted into the diode string D1, D2, . . . , Dnxe2x88x921, Dn to eliminate the leakage current through the forward-biased diode string. Another issue when cascading diodes in a diode string is the reduction of the turn-on voltage drop across the diode string at higher temperatures. The temperature effect can be seen in equation (4), where the temperature coefficient of VD is negative, because       nEg0    q    =      1.206    ⁢          xe2x80x83        ⁢    Volts  
is larger than VD (around 0.55 Volts to about 0.65 Volts for forward current of 1 xcexcA to about 10 xcexcA at room temperature). Thus even more cascaded diodes are required in the diode string D1, D2, . . . , Dnxe2x88x921, Dn to control a reasonable leakage current in the VDD-to-VSS ESD clamp circuit at a higher temperature. The additional number of cascaded diodes will occupy a large silicon area of an IC device.
2.2. Design on the Diode String to Reduce Leakage Current
To reduce the leakage current of a PNP-based diode string, especially operating in a high-temperature environment, three designs were shown by T. J. Maloney and S. Dabral in xe2x80x9cNovel clamp circuits for IC power supply protection,xe2x80x9d Proc. of EOS/ESD Symp., pp. 1.1.1 to 1.1.12 (1995) [15], which are re-drawn in FIGS. 5A-5C.
FIG. 5A shows a Cladded diode string, which is a modification of the circuit of Maloney [12]), FIG. 12, page 1.1.6.
FIG. 5B shows a Boosted diode string, which is a modification of the circuit of Maloney [12]), FIG. 15, page 1.1.7.
FIG. 5C shows a Cantilever diode string, which is a modification of the circuit of Maloney [12]), FIG. 18, page 1.1.9 and U.S. Pat. No. 5,530,612 of Maloney for xe2x80x9cElectrostatic Discharge Protection Circuits Using Biased and Terminated PNP Transistor Chains, FIG. 22 [17].
2.2.1 The Cladded Diode String
Referring to FIG. 5A, as the number of cascaded diodes D1, D2 . . . D6 increases, there is a declining incremental voltage across the PNP-based diode string because there is a lower current density through the latter diode stages. A way to solve that problem was provided by augmenting the diode string with a bias network to distribute small but significant forward current into the distal diode stages, D4, D5 and D6. The cladded diode string of series connected diodes D1, D2 . . . D6 shown connected between VDD voltage and the VSS ground connection in FIG. 5A embodies this concept with two long channel PMOS transistors M1 and M2 operating in the triode region, which are used as resistors to provide forward current from power rail VDD to the distal cascaded diodes D3 and D4 from transistor M1 and D5 and D6 from transistor M2. NMOS transistor M3 is used as a resistive connection between VSS (ground) and the gates of M1 and M2. The source/drain circuits of transistors M1 and M2 are connected in series starting at the power rail VDD with the junction thereof connected to the junction between diodes D2 and D3. The other end of the source drain circuit is connected to the junction between diodes D4 and D5. The gate electrodes of transistors M1 and M2 are connected to the shorted drain/gate electrode of NMOS transistor M3 and the source of transistor M3 is connected to the cathode of diode D6 with both being connected to ground VSS. The device dimensions (W/L) of transistors M1, M2, and M3, are based on the previous design in the Maloney et al. [15] as 1.8/40, 1.8/40, and 1.8/5 (xcexcm/xcexcm), respectively, which are simulated by the SPICE program with 0.35 xcexcm 1P3M SPICE parameters.
2.2.2 The Boosted Diode String
In FIG. 5B, a boosted diode string (a series connected string of diodes D1-D8) is shown embodying a similar concept to the cladded diode string, employing distribution of current to distal cascaded diodes D6-D8 in the series connected string of diodes D1-D8. The source/drain circuits of two very long channel transistors M1 and M2 are connected in series between the power rails VDD and VSS in parallel with the diodes D1-D8. The drain region and the gate electrode of transistor M1 are shorted together. Two very long channel transistors M1 and M2, are always on, but the two very long channel devices PMOS transistors M1 and M2 do not draw significant leakage currents. The drain of NMOS transistor M3 is connected to power rail VDD. The source of NMOS transistor M3 is connected to the node between diode D5 and diode D6. The gate electrode of transistor M3 is connected to the junction between the source/drain circuits of transistor M1 and M2.
When the voltage of the source node of M3 falls below the threshold voltage of M3 with respect to its gate voltage while at a high temperature, the source follower transistor M3 (which is a stronger device, capable of withstanding many micro-amperes of current) turns on until the distal part of the diode string is replenished adequately.
But, transistor M3 is completely off or provides only very small currents at lower temperatures. The device dimensions (W/L) of M1, M2, and M3, based on T. Maloney et al. [15] and SPICE simulations, are 1.8/40, 1.8/40, and 200/1 (xcexcm/xcexcm), respectively.
2.2.3 The Cantilever Diode String
FIG. 5C shows a circuit diagram which illustrates the design concept of the cantilevered diode string. The key to concept is to block the diode string D1-D6 from VSS in normal operation, which helps to avoid the amplification effect of multi-stage Darlington beta (xcex2) gain among the vertical PNP transistors in the diode string causing the more leakage current into the P-substrate (not shown). But, when an ESD condition occurs, the diode string D1-D6 between VDD-to-VSS is turned on by a detection circuit which turns on transistor M1 to bypass the ESD current to ground.
In FIG. 5C, the PMOS transistor M1 is used as the termination of the diode string D1-D6 from VSS in normal condition but sinks a substantial amount of current when an ESD pulse is occurring. PMOS transistor M2 and capacitor C comprise the RC-based ESD detection circuit which distinguishes between an ESD condition and a normal condition, and turns transistor M1 on or off correctly. The PMOS transistors M3 and M4 are long channel devices used as the bias network as that shown in the cladded diode string design. Transistor M3 connects power rail VDD to the node between diodes D3 and D4 in the diode string D1, D2 . . . D6. A small NMOS transistor M5 provides a ground connection without allowing a power supply voltage across a single thin gate oxide. The device dimensions (W/L) of M1, M2, M3, M4 and M5, which are based on the previous report by T. Maloney [15] and the SPICE simulations, are 200/1, 1.8/40, 1.8/40, 1.8/40 and 1.8/5 xcexcm/xcexcm), respectively.
In accordance with this invention, a new power supply ESD clamp circuit with an SCR (Silicon Controlled Rectifier) device and a diode string is provided. The present invention can apply excellent ESD protection performance of an SCR and diode string circuit for a power supply ESD clamp, but without the disadvantages of the leakage current problem illustrated by the diode string designs [12]-[15] and the latchup issue in the SCR device from power rail VDD to power rail VSS.